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altera corporation 709 max 5000 pr ogrammab le logic de vice f amil y ma y 1999, ver . 5 data sheet a-ds-m5000-05 9 max 5000 fea tur es... n advanced multiple array matrix (max ? ) 5000 architecture combining speed and ease-of-use of pal devices with the density of programmable gate arrays n complete family of high-performance, erasable cmos eprom erasable programmable logic devices (eplds) for designs ranging from fast 28-pin address decoders to 100-pin lsi custom peripherals n 600 to 3,750 usable gates (see table 1 ) n fast, 15-ns combinatorial delays and 76.9-mhz counter frequencies n configurable expander product-term distribution allowing more than 32 product terms in a single macrocell n 28 to 100 pins available in dual in-line package (dip), j-lead chip carrier, pin-grid array (pga), and quad flat pack (qfp) packages n programmable registers providing d, t, jk, and sr flipflop functionality with individual clear, preset, and clock controls n programmable security bit for protection of proprietary designs n software design support featuring the altera ? max+plus ? ii development system on windows-based pcs, as well as sun sparcstation, hp 9000 series 700/800, and ibm risc system/6000 workstations table 1. max 5000 device feature s feature epm503 2 epm506 4 epm5128 epm513 0 epm519 2 usable gates 600 1,250 2,500 2,500 3,750 macrocells 32 64 128 128 192 logic array blocks (labs) 1 4 8 8 12 expanders 64 128 256 256 384 routing global pia pia pia pia maximum user i/o pins 24 36 60 84 72 t pd (ns) 15 25 25 25 25 t asu (ns) 4 4 4 4 4 t co (ns) 10 14 14 14 14 f cnt (mhz) 76.9 50 50 50 50
710 altera corporation max 5000 pr ogrammab le logic de vice f amil y data sheet ...and more features n programming support with alteras master programming unit (mpu) or programming hardware from third-party manufacturers n additional design entry and simulation support provided by edif, library of parameterized modules (lpm), verilog hdl, vhdl, and other interfaces to popular eda tools from manufacturers such as cadence, exemplar logic, mentor graphics, orcad, synopsys, synplicity, and viewlogic general descriptio n the max 5000 family combines innovative architecture and advanced process technologies to offer optimum performance, flexibility, and the highest logic-to-pin ratio of any general-purpose programmable logic device (pld) family. the max 5000 family provides 600 to 3,750 usable gates, pin-to-pin delays as fast as 15 ns, and counter frequencies of up to 76.9 mhz (see table 2 ). the max 5000 architecture supports 100 % ttl emulation and high- density integration of multiple ssi, msi, and lsi logic functions. for example, an epm5192 device can replace over 100 74- series devices; it can integrate complete subsystems into a single package, saving board area and reducing power consumption. max 5000 eplds are available in a wide range of packages (see table 3 ), including the following: n windowed ceramic and plastic dual in- line (cerdip and pdip) n plastic j-lead chip carrier (plcc) n windowed ceramic pin-grid array (pga) n plastic quad flat pack (pqfp) table 2. max 5000 device speed grades device spee d ( t pd1 ) 15 ns 20 ns 25 ns 30 ns 35 ns epm503 2 v v v epm506 4 v v v epm512 8 v v v epm513 0 v v epm519 2 v v
altera corporation 711 max 5000 pr ogrammab le logic de vice f amil y data sheet 9 max 5000 max 5000 eplds have between 32 and 192 macrocells that are combined into groups called logic array blocks (labs). each macrocell has a programmable- and /fixed- or array and a configurable register that provides d, t, jk, or sr operation with independent programmable clock, clear, and preset functions. to build complex logic functions, each macrocell can be supplemented with shareable expander product terms (shared expanders) to provide more than 32 product terms per macrocell. the max 5000 family is supported by alteras max+plus ii development system, a single, integrated package that offers schematic, textincluding the altera hardware description language (ahdl) and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. the max+plus ii system provides edif 2 0 0 and 3 0 0, lpm, vhdl, verilog hdl, and other interfaces for additional design entry and simulation support from other industry-standard pc- and unix workstation-based eda tools. the max+plus ii software runs on windows-based pcs as well as sun sparcstation, hp 9000 series 700/800, and ibm risc system/6000 workstations. f for more information on the max+plus ii development system, see the max+plus ii programmable logic development system & software data sheet . functional description this section provides a functional description of max 5000 eplds, which have the following architectural features: n logic array blocks n macrocells n clocking options n expander product terms n programmable interconnect array n i/o control blocks table 3. max 5000 pin count & packag e options device pin count cerdip pdip plcc pga pqfp epm5032 28 28 28 epm5064 44 epm5128 68 68 epm5130 84 100 100 epm5192 84 84
712 altera corporation max 5000 pr ogrammab le logic de vice f amil y data sheet the max 5000 ar chitectur e is based on the concept of linking high- performance, ? exible logic array modules called labs. multiple labs ar e linked via the pr ogrammable inter connect array (pia), a global bus that is fed by all i/o pins and macr ocells . in addition to these basic elements, the max 5000 ar chitectur e includes 8 to 20 dedicated inputs, each of which can be used as a high-speed, general-purpose inpu t. alternatively , one of the dedicated inputs can be used as a high-speed global clock for r egisters. logic array block s max 5000 eplds contain 1 to 12 labs. the epm5032 has a single lab, while the epm5064, epm5128, epm5130, and epm5192 contain multiple labs. each lab consists of a macrocell array and an expander product- term array (see figure 1 ). the number of macrocells and expanders in the arrays varies with each device. figure 1. max 5000 architec tu re e x p a n d e r p r o d u c t - t e r m a r r a y m a c r o c e l l a r r a y l a b a p i a 4 t o 1 6 i / o p i n s p e r l a b t o a l l o t h e r l a b s i / o c o n t r o l b l o c k 8 t o 2 0 d e d i c a t e d i n p u t s f e e d b a c k f r o m i / o p i n s t o l a b ( s i n g l e - l a b d e v i c e s o n l y ) p i a i n m u l t i - l a b d e v i c e s o n l y 1 6 2 4 l a b i n t e r c o n n e c t
altera corporation 713 max 5000 pr ogrammab le logic de vice f amil y data sheet 9 max 5000 macrocells are the primary resource for logic implementation. additional logic capability is available from expanders, which can be used to supplement the capabilities of any macrocell. the expander product-term array consists of a group of unallocated, inverted product terms that can be used and shared by all macrocells in the lab to create combinatorial and registered logic. these flexible macrocells and shareable expanders facilitate variable product-term designs without the inflexibility of fixed product-term architectures. all macrocell outputs are globally routed within an lab via the lab interconnect. the outputs of the macrocells also feed the i/o control block, which consists of groups of programmable tri-state buffers and i/o pins. in the epm5064, epm5128, epm5130, and epm5192 devices, multiple labs are connected by a pia. all macrocells feed the pia to provide efficient routing for high-fan-in designs. macrocells th e max 5000 macrocell consists of a programmable logic array and an independently configurable register (see figure 2 ). the register can be programmed to emulate d, t, jk, or sr operation, as a flow-through latch, or bypassed for combinatorial operation. combinatorial logic is implemented in the programmable logic array, in which three product terms that are or ed together feed one input to an xor gate. the second input to the xor gate is used for complex xor arithmetic logic functions and for de morgans inversion. the output of the xor gate feeds the pr ogrammable r egister or bypasses it for combinatorial operation.
714 altera corporation max 5000 pr ogrammab le logic de vice f amil y data sheet figure 2. max 5000 device macrocell additional product terms (called secondary product terms) are used to control the output enabl e, prese t, clea r, and cloc k signals. preset and clear product terms drive the active-low asynchronous preset and asynchronous clear inputs to the configurable flipflop. the clock product term allows each register to have an independent clock and supports positive- and negative-edge-triggered operation. macrocells that drive an output pin can use the output enable product term to control the active- high tri-state buffer in the i/o control block. the max 5000 macrocell configurability makes it possible to efficiently integrate complete subsystems into a single device. clocking optio ns each lab supports either global or array clocking. global clocking is provided by a dedicated clock signal ( clk ) that offers fast clock-to-output delay times. because each lab has one global clock, all flipflop clocks within the lab can be positive-edge-triggered from the clk pin. if the clk pin is not used as a global clock, it can be used as a high-speed dedicated input. prn clrn q 8 or 20 dedicated inputs 32 or 64 expander product t erms 24 programmable interconnect signals (multi-lab devices only) output enable preset clear global clock (one per lab) programmable register i/o feedback macrocell feedback d/t array clock logic array to i/o control block from i/o control block to i/o control block
altera corporation 715 max 5000 pr ogrammab le logic de vice f amil y data sheet 9 max 5000 in the array clockin g mode, each flipflop is clocked by a product term. any input pin or internal logic can be used as a clock source. array clocking allows each flipflop to be configured for positive- or negative- edge-triggered operation, giving the macrocell increased flexibility. systems that require multiple clocks are easily integrated into max 5000 eplds. each flipflop in an lab can be clocked by a different array-generated clock; however, global and array clocking modes cannot be mixed in the same lab. expander product t er ms while most logic functions can be implemented with the product terms available in each macrocell, some logic functions are more complex and require additional product terms. although additional macrocells can be used to supply the needed logic resources, the max 5000 architecture can also use shared expander product terms that provide additional product terms directly to any macrocell in the same lab. these expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed. each lab has 32 shared expanders (except for epm5032 devices, which have 64). the expanders can be viewed as a pool of uncommitted product terms. the expander product-term array (see figure 3 ) contains unallocated, inverted product terms that feed the macrocell array. expanders can be used and shared by all product terms in the lab. wherever extra logic is needed (including register control functions), expanders can be used to implement the logic. these expanders provide the flexibility to implement register- and product-term-intensive designs in max 5000 eplds.
716 altera corporation max 5000 pr ogrammab le logic de vice f amil y data sheet figure 3. expander product t erms expanders are fed by all signals in the lab. one expander can feed all macrocells in the lab or multiple product terms in the same macrocell. because expanders also feed the secondary product terms of each macrocell, complex logic functions can be implemented without using additional macrocells. a small delay ( t sexp ) is incurred when shared expanders are used. pro grammable interconnect arra y the multi-lab max 5000 devicesepm5064, epm5128, epm5130, and epm5192 devicesuse a pia to route signals between the various labs. the pia, which is fed by all macrocell and i/o pin feedbacks, routes only the signals required for implementing logic in an lab. while the routing delays of segmented routing schemes in masked or field-programmable gate arrays (fpgas) are cumulative, variable, and path-dependent, the max 5000 pia has a fixed delay. the pia thus eliminates skew between signals and makes timing performance easy to predict. i/o c ontrol blocks each lab has an i/o control block that allows each i/o pin to be individually configured for input, output, or bidirectional operation (see figure 4 ). the i/o control block is fed by the macrocell array. a dedicated macrocell product term controls a tri-state buffer, which drives the i/o pin. 8 or 20 dedicated inputs 32 or 64 expander product t erms 24 programmable interconnect signals (multi-lab devices only) t o macrocell array macrocell fee d backs
altera corporation 717 max 5000 pr ogrammab le logic de vice f amil y data sheet 9 max 5000 figure 4. i/o control block the max 5000 architecture provides d ual i/o feedback in which macrocell and i/o pin feedbacks are independent, allowing maximum flexibility. when an i/o pin is configured as an input, the associated macrocell can be used for buried logic. using an i/o pin as an input in single- lab devices reduces the number of available expanders by two. in multi- lab devices, i/o pins feed the pia directly. design securit y all max 5000 eplds contain a programmable secur ity bit that controls access to the data programmed into the device. when this bit is programmed, a proprietary design implemented in the device cannot be copied or retrieved. this feature provides a high level of design security, because programmed data within eprom cells is invisible. the security bit that controls this function, as well as all other program data, is reset only when the device is erased. generic t estin g m ax 5000 eplds are fully functionally tested. complete testing of each programmable eprom bit and all internal logic elements ensures 100 % programming yield. test patterns can be used and then erased during early stages of the device production flow. the devices also contain on- board logic test circuitry to allow verification of function and ac specifications during the production flow. ac test measurements are taken under conditions equivalent to those in figure 5 . o e c o n t r o l ( f r o m m a c r o c e l l p r o d u c t ) f r o m m a c r o c e l l m a c r o c e l l f e e d b a c k i / o p i n f e e d b a c k
718 altera corporation max 5000 pr ogrammab le logic de vice f amil y data sheet figure 5. ac t est conditions devi ce programmin g all max 5000 eplds can be programmed on windows- based pcs with the max+plus ii programmer, an altera logic programmer card, the master programming unit (mpu), and the appropriate device adapter. the mpu checks continuity to ensure adequate electrical contact between the adapter and the device. f for more information, see the altera programming hardware data sheet . the max+plus ii software can use text- or waveform-format test vectors created with the max+plus ii text editor or waveform editor to test a programmed device. for added design verification, designers can perform functional testing to compare the functional behavior of a max 5000 epld with the simulation results. this feature requires a device adapter with the plm- prefix. data i/o, bp microsystems, and other programming hardware manufacturers also offer programming support for altera devices. f for more information, see programming hardware manufacturers. qfp carrier & development socket max 5000 devices in 100-pin qfp packages are shipped in special plastic carriers to protect the qfp leads. each carrier can be used with a prototype development socket and programming hardware available from altera or third-party programming manufacturers such as data i/o and bp microsystems. this carrier technology makes it possible to program, test, erase, and reprogram devices without exposing the leads to mechanical stress. f for detailed information and carrier dimensions, refer to the qfp carrier & development socket data sheet and application note 71 (guidelines for handling j-lead & qfp devices) . power supply transients can affect ac measurements. simultaneous transitions of multiple outputs should be avoided for accurate measurement. threshold tests must not be per formed under ac conditions. large-amplitude, fast ground- current transients normally occur as the device outputs discharge the load capacitances. when these transients ? ow through the parasitic inductance between the device ground pin and the test system ground, signi? cant reductions in obser vable noise immunity can result. vcc to t est system c1 (includes jig capacitance) de vice input r ise and f all times < 3 ns 464 w de vice output 250 w
altera corporation 719 max 5000 pr ogrammab le logic de vice f amil y data sheet 9 max 5000 operating conditions tables 4 through 8 provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for max 5000 devices. table 4. max 5000 device absolute maximum ratings note (1) symbol parameter conditions min max unit v cc supply voltage with respect to ground (2) C2.0 7.0 v v i dc input voltage C2.0 7.0 v i out dc output current, per pin C25 25 ma t stg storage temperature no bias C65 135 c t amb ambient temperature under bias C65 135 c t j junction temperature ceramic packages, under bias 150 c plastic packages, under bias 135 c table 5. max 5000 device recommended operating conditions symbol parameter conditions min max unit v cc supply voltage (3) , (4) 4.75 (4.5) 5.25 (5.5) v v i input voltage C0.3 v cc +0.3 v v o output voltage 0 v cc v t a ambient temperature for commercial use 0 70 c for industrial use C40 85 c t r input rise time 100 ns t f input fall time 100 ns table 6. max 5000 device dc operating conditions note (5) symbol parameter conditions min typ max unit v ih high-level input voltage 2.0 v cc + 0.3 v v il low-level input voltage C0.3 0.8 v v oh high-level ttl output voltage i oh = C4 ma dc (6) 2.4 v v ol low-level output voltage i ol = 8 ma dc (6) 0.45 v i i leakage current of dedicated inputs v i = v cc or ground C10 10 m a i oz i/o pin tri-state output off-state current v o = v cc or ground C40 40 m a table 7. epm5032 max 5000 device capacitance symbol parameter conditions min max unit c in input pin capacitance v in = 0 v, f = 1.0 mhz 10 pf c i/o i/o pin capacitance v out = 0 v, f = 1.0 mhz 12 pf
720 altera corporation max 5000 pr ogrammab le logic de vice f amil y data sheet notes to tables: (1) see the operating requirements for altera devices data sheet in this data book. (2) minimum dc input is C0.3 v. during transitions, the inputs may undershoot to C2.0 v or overshoot to 7.0 v for input currents less than 100 ma and periods shorter than 20 ns. (3) numbers in parentheses are for industrial-temperature-range devices. (4) maximum v cc rise time for max 5000 devices is 10 ms. (5) typical values are for t a = 25 c and v cc = 5.0 v. (6) the i oh parameter refers to high-level ttl output current; the i ol parameter refers to low-level ttl output current. figure 6 shows typical output drive characteristics of max 5000 devices. figure 6. output drive characteristics of max 5000 devices t iming mode l ma x 5000 epld timing can be analyzed with the max+plus ii software, with a variety of other industry-standard eda simulators and timing analyzers, or with the timing model shown in figure 7 . max 5000 eplds have fixed internal delays that allow the designer to determine the worst-case timing for any design. the max+plus ii software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for system-level performance evaluation. table 8. epm5064, epm5128, epm5130 & epm5192 max 5000 device capacitance symbol parameter conditions min max unit c in input pin capacitance v in = 0 v, f = 1.0 mhz 10 pf c i/o i/o pin capacitance v out = 0 v, f = 1.0 mhz 20 pf v o o u t p u t v o l t a g e ( v ) 5 0 1 5 0 1 0 0 i o l i o h v c c i n t = 5 . 0 v v c c i o = 5 . 0 v r o o m t e m p e r a t u r e 1 t y p i c a l i o o u t p u t c u r r e n t ( m a ) 2 0 0 2 5 0 5 4 3 2 3 . 8
altera corporation 721 max 5000 pr ogrammab le logic de vice f amil y data sheet 9 max 5000 figure 7. max 5000 t iming mod el i/o dela y t io logic arr a y dela y t lad input dela y t in logic arr a y control dela y t la c f eedbac k dela y t fd output dela y t od t xz t zx register dela y t rd t comb t la tch t clr t pre t su t h shared expander dela y t sexp array clock delay t ic global clock delay t ics single-lab eplds pia dela y t pia logic arr a y dela y t lad input dela y t in logic arr a y control dela y t la c feedbac k dela y t fd output dela y t od t xz t zx register dela y t rd t comb t la tch t clr t pre t su t h i/o dela y t io shared expander dela y t sexp array cloc k dela y t ic global cloc k dela y t ics multi-lab eplds
722 altera corporation max 5000 pr ogrammab le logic de vice f amil y data sheet t iming information can be derived fr om the timing model and parameters for a particular epld. external timing parameters ar e calculated with the sum of internal parameters and r epr esent pin-to-pin timing delays. figur e 8 shows the internal timing r elationship for internal and external delay parameters. f see application note 78 (understanding max 5000 & classic t iming) for mor e information on epld timing.
altera corporation 723 max 5000 pr ogrammab le logic de vice f amil y data sheet 9 max 5000 figure 8. switching w aveform s in multi-lab eplds, i/o pins that are used as inputs traverse the pia. t r and t f < 3 ns. inputs are driven at 3 v for a logic high and 0 v for a logic low . t in high-impedance state output pin t xz t zx t od t rd t f t ch t cl t r t in t ic s t su t h t f t r t a ch t a cl t in t ic t rd , t l a tch t fd t fd t p ia t io t sexp t od t comb t su t h t clr , t pre input mode array clock mode global clock mode output mode t la c , t lad i/o pin expander arr a y dela y logic arr a y input logic arr a y output output pin input pin cloc k into logic arr a y data from logic arr a y register output to local lab logic arr a y register output to another lab cloc k pin cloc k from logic arr a y global cloc k pin global cloc k at register data from logic arr a y cloc k from logic arr a y data from logic arr a y
724 altera corporation max 5000 pr ogrammab le logic de vice f amil y data sheet tables 9 and 10 show epm 5032 timing parameters. table 9. epm5032 external timing parameters note (1) symbol parameter conditions speed grade unit -15 -20 -25 min max min max min max t pd1 input to non-registered output c1 = 35 pf 15.0 20.0 25.0 ns t pd2 i/o input to non-registered output c1 = 35 pf 15.0 20.0 25.0 ns t su global clock setup time 9.0 12.0 15.0 ns t h global clock hold time 0.0 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 10.0 12.0 15.0 ns t ch global clock high time 6.0 7.0 8.0 ns t cl global clock low time 6.0 7.0 8.0 ns t asu array clock setup time 5.0 6.0 8.0 ns t ah array clock hold time 5.0 6.0 8.0 ns t aco1 array clock to output delay c1 = 35 pf 15.0 18.0 22.0 ns t ach array clock high time (2) 6.0 7.0 9.0 ns t acl array clock low time 7.0 9.0 11.0 ns t odh output data hold time after clock c1 = 35 pf (3) 1.0 1.0 1.0 ns t cnt minimum global clock period 13.0 16.0 20.0 ns f cnt maximum internal global clock frequency (4) 76.9 62.5 50.0 mhz t acnt minimum array clock period 13.0 16.0 20.0 ns f acnt maximum internal array clock frequency (4) 76.9 62.5 50.0 mhz f max maximum clock frequency (5) 83.3 71.4 62.5 mhz
altera corporation 725 max 5000 pr ogrammab le logic de vice f amil y data sheet 9 max 5000 table 10. epm5032 internal tim ing parameters note (6) symbol parameter conditions speed grade unit -15 -20 -25 min max min max min max t in input pad and buffer delay 3.0 5.0 7.0 ns t io i/o input pad and buffer delay 3.0 5.0 7.0 ns t sexp expander array delay 8.0 10.0 15.0 ns t lad logic array delay 7.0 10.0 13.0 ns t lac logic control array delay 4.0 4.0 4.0 ns t od output buffer and pad delay c1 = 35 pf 4.0 4.0 4.0 ns t zx output buffer enable delay c1 = 35 pf 7.0 7.0 7.0 ns t xz output buffer disable delay c1 = 5 pf 7.0 7.0 7.0 ns t su register setup time 4.0 4.0 5.0 ns t latch flow-through latch delay 1.0 1.0 1.0 ns t rd register delay 1.0 1.0 1.0 ns t comb combinatorial delay 1.0 1.0 1.0 ns t h register hold time 5.0 8.0 10.0 ns t ic array clock delay 7.0 8.0 10.0 ns t ics global clock delay 2.0 2.0 3.0 ns t fd feedback delay 1.0 1.0 1.0 ns t pre register preset time 5.0 6.0 9.0 ns t clr register clear time 5.0 6.0 9.0 ns
726 altera corporation max 5000 pr ogrammab le logic de vice f amil y data sheet table 11. epm5064, epm5128, epm5130 & epm5192 external timing parameters note (1) symbol parameter conditions speed grade (7) unit -1 -2 epm5064 epm5128 epm5130 epm5192 min max min max min max t pd1 input to non-registered output c1 = 35 pf 25.0 30.0 35.0 ns t pd2 i/o input to non-registered output c1 = 35 pf 40.0 45.0 55.0 ns t su global clock setup time 15.0 20.0 25.0 ns t h global clock hold time 0.0 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 14.0 16.0 20.0 ns t ch global clock high time 8.0 10.0 12.5 ns t cl global clock low time 8.0 10.0 12.5 ns t asu array clock setup time 5.0 6.0 10.0 ns t ah array clock hold time 6.0 8.0 10.0 ns t aco1 array clock to output delay c1 = 35 pf 25.0 30.0 35.0 ns t ach array clock high time (2) 11.0 14.0 16.0 ns t acl array clock low time 9.0 11.0 14.0 ns t cnt minimum global clock period 20.0 25.0 30.0 ns t odh output data hold time after clock c1 = 35 pf (3) 2.0 2.0 2.0 ns f cnt maximum internal global clock frequency (4) 50.0 40.0 33.3 mhz t acnt minimum array clock period 20.0 25.0 30.0 ns f acnt maximum internal array clock frequency (4) 50.0 40.0 33.3 mhz f max maximum clock frequency (5) 62.5 50.0 40.0 mhz
altera corporation 727 max 5000 pr ogrammab le logic de vice f amil y data sheet 9 max 5000 notes to tables: (1) operating conditions are specified in table 5 on page 719 . (2) this parameter is measured with a positive-edge-triggered clock at the register. for negative-edge clocking, the t ach and t acl parameters must be swapped. (3) this parameter is a guideline that is sample-tested only. it is based on extensive device characterization and applies to both global and array clocking. (4) for epm5032 devices, this parameter is measured with a 32-bit counter programmed into the device. for epm5064, epm5128, epm5130, and epm5192 devices, this parameter is measured with a 16-bit counter programmed into each lab. (5) the f max values represent the highest frequency for pipelined data. (6) for information on internal timing parameters, refer to application note 78 (understanding max 5000 & classic t iming) in this data book. (7) the epm 5064, epm 5128, epm 5130, and epm 5132 are listed without speed grade designators. table 12. epm5064, epm5128, epm5130 & epm5192 internal timing parameters note (6) symbol parameter conditions speed grade (7) unit -1 -2 epm5064 epm5128 epm5130 epm5192 min max min max min max t in input pad and buffer delay 5.0 7.0 11.0 ns t io i/o input pad and buffer delay 6.0 6.0 11.0 ns t sexp expander array delay 12.0 14.0 20.0 ns t lad logic array delay 12.0 14.0 14.0 ns t lac logic control array delay 10.0 12.0 13.0 ns t od output buffer and pad delay c1 = 35 pf 5.0 5.0 6.0 ns t zx output buffer enable delay c1 = 35 pf 10.0 11.0 13.0 ns t xz output buffer disable delay c1 = 5 pf 10.0 11.0 13.0 ns t su register setup time 6.0 8.0 12.0 ns t latch flow-through latch delay 3.0 4.0 4.0 ns t rd register delay 1.0 2.0 2.0 ns t comb combinatorial delay 3.0 4.0 4.0 ns t h register hold time 4.0 6.0 8.0 ns t ic array clock delay 14.0 16.0 16.0 ns t ics global clock delay 3.0 2.0 1.0 ns t fd feedback delay 1.0 1.0 2.0 ns t pre register preset time 5.0 6.0 7.0 ns t clr register clear time 5.0 6.0 7.0 ns t pia programmable interconnect array delay 14.0 16.0 20.0 ns
728 altera corporation max 5000 pr ogrammab le logic de vice f amil y data sheet figure 9 shows the typical supply current versus frequency of max 5000 devices. figure 9. i cc vs. frequency for max 5000 devices (part 1 of 2) v c c = 5 . 0 v r o o m t e m p e r a t u r e 1 0 0 h z 1 k h z 1 0 k h z 1 0 0 k h z 1 m h z 1 0 m h z 4 0 1 2 0 f r e q u e n c y 2 4 0 1 6 0 2 0 0 8 0 7 6 . 9 m h z e p m 5 0 3 2 v c c = 5 . 0 v r o o m t e m p e r a t u r e 1 0 0 h z 1 k h z 1 0 k h z 1 0 0 k h z 1 m h z 1 0 m h z 5 0 f r e q u e n c y 2 0 0 1 0 0 1 5 0 5 0 m h z 5 0 m h z e p m 5 1 2 8 e p m 5 1 3 0 v c c = 5 . 0 v r o o m t e m p e r a t u r e 1 k h z 1 0 k h z 1 0 0 k h z 1 m h z 1 0 m h z 1 0 0 f r e q u e n c y i c c a c t i v e ( m a ) t y p i c a l 4 0 0 2 0 0 3 0 0 1 0 0 h z v c c = 5 . 0 v r o o m t e m p e r a t u r e 1 k h z 1 0 k h z 1 0 0 k h z 1 m h z 1 0 m h z 1 0 0 f r e q u e n c y 5 0 0 2 0 0 3 0 0 5 0 m h z 4 0 0 1 0 0 h z e p m 5 0 6 4 i c c a c t i v e ( m a ) t y p i c a l i c c a c t i v e ( m a ) t y p i c a l i c c a c t i v e ( m a ) t y p i c a l
altera corporation 729 max 5000 pr ogrammab le logic de vice f amil y data sheet 9 max 5000 figure 9. i cc vs. frequency for max 5000 devices (part 2 of 2) device pin-o uts t ables 13 thr ough 22 show the pin names and numbers for the pins in each max 5000 device package. 1 k h z 1 0 k h z 1 0 0 k h z 1 m h z 1 0 m h z f r e q u e n c y 5 0 0 5 0 m h z 1 0 0 h z e p m 5 1 9 2 4 0 0 3 0 0 2 0 0 1 0 0 v c c = 5 . 0 v r o o m t e m p e r a t u r e t y p i c a l i c c a c t i v e ( m a )
730 altera corporation max 5000 pr ogrammab le logic de vice f amil y data sheet table 13. epm5032 dedicated pin-outs pin name 28-pin plcc 28-pin dip input/clk 9 2 input 6, 7, 8, 20, 21, 22, 23 1, 13, 14, 15, 16, 27, 28 gnd 15, 28 8, 21 vcc 1, 14 7, 22 table 14. epm5032 i/o pin-outs lab mc 28-pin plcc 28-pin dip lab mc 28-pin plcc 28-pin dip a 1 10 3 b 17 24 17 2 C C 18 C C 3 11 4 19 25 18 4 C C 20 C C 5 12 5 21 26 19 6 C C 22 C C 7 13 6 23 27 20 8 C C 24 C C 9 16 9 25 2 23 10 C C 26 C C 11 17 10 27 3 24 12 C C 28 C C 13 18 11 29 4 25 14 C C 30 C C 15 19 12 31 5 26 16 C C 32 C C
altera corporation 731 max 5000 pr ogrammab le logic de vice f amil y data sheet 9 max 5000 table 15. epm5064 dedicated pin-outs pin name 44-pin plcc input/clk 34 input 9, 11, 12, 13, 31, 33, 35 gnd 10, 21, 32, 43 vcc 3, 14, 25, 36 table 16. epm5064 i/o pin-outs (part 1 of 2) lab mc 44-pin plcc lab mc 44-pin plcc a 1 2 b 17 15 2 4 18 16 3 5 19 17 4 6 20 18 5 7 21 19 6 8 22 20 7 C 23 22 8 C 24 23 9 C 25 C 10 C 26 C 11 C 27 C 12 C 28 C 13 C 29 C 14 C 30 C 15 C 31 C 16 C 32 C
732 altera corporation max 5000 pr ogrammab le logic de vice f amil y data sheet c 33 24 d 49 37 34 26 50 38 35 27 51 39 36 28 52 40 37 29 53 41 38 30 54 42 39 C 55 44 40 C 56 1 41 C 57 C 42 C 58 C 43 C 59 C 44 C 60 C 45 C 61 C 46 C 62 C 47 C 63 C 48 C 64 C table 16. epm5064 i/o pin-outs (part 2 of 2) lab mc 44-pin plcc lab mc 44-pin plcc
altera corporation 733 max 5000 pr ogrammab le logic de vice f amil y data sheet 9 max 5000 table 17. epm5128 dedicated pin-outs pin name 68-pin plcc 68-pin pga input/clk 1 b6 input 2, 32, 34, 35, 36, 66, 68 a6, l4, l5, l6, k6, a8, a7 gnd 16, 33, 50, 67 b7, e2, g10, k5 vcc 3, 20, 37, 54 b5, e10, g2, k7 table 18. epm5128 i/o pin-outs (part 1 of 3) lab mc 68-pin plcc 68-pin pga lab mc 68-pin plcc 68-pin pga a 1 4 a5 b 17 12 c2 2 5 b4 18 13 c1 3 6 a4 19 14 d2 4 7 b3 20 15 d1 5 8 a3 21 17 e1 6 9 a2 22 C C 7 10 b2 23 C C 8 11 b1 24 C C 9 C C 25 C C 10 C C 26 C C 11 C C 27 C C 12 C C 28 C C 13 C C 29 C C 14 C C 30 C C 15 C C 31 C C 16 C C 32 C C
734 altera corporation max 5000 pr ogrammab le logic de vice f amil y data sheet c 33 18 f2 e 65 38 l7 34 19 f1 66 39 k8 35 21 g1 67 40 l8 36 22 h2 68 41 k9 37 23 h1 69 42 l9 38 C C 70 43 l10 39 C C 71 44 k10 40 C C 72 45 k11 41 C C 73 C C 42 C C 74 C C 43 C C 75 C C 44 C C 76 C C 45 C C 77 C C 46 C C 78 C C 47 C C 79 C C 48 C C 80 C C d 49 24 j2 f 81 46 j10 50 25 j1 82 47 j11 51 26 k1 83 48 h10 52 27 k2 84 49 h11 53 28 l2 85 51 g11 54 29 k3 86 C C 55 30 l3 87 C C 56 31 k4 88 C C 57 C C 89 C C 58 C C 90 C C 59 C C 91 C C 60 C C 92 C C 61 C C 93 C C 62 C C 94 C C 63 C C 95 C C 64 C C 96 C C table 18. epm5128 i/o pin-outs (part 2 of 3) lab mc 68-pin plcc 68-pin pga lab mc 68-pin plcc 68-pin pga
altera corporation 735 max 5000 pr ogrammab le logic de vice f amil y data sheet 9 max 5000 g 97 52 f10 h 113 58 c10 98 53 f11 114 59 c11 99 55 e11 115 60 b11 100 56 d10 116 61 b10 101 57 d11 117 62 a10 102 C C 118 63 b9 103 C C 119 64 a9 104 C C 120 65 b8 105 C C 121 C C 106 C C 122 C C 107 C C 123 C C 108 C C 124 C C 109 C C 125 C C 110 C C 126 C C 111 C C 127 C C 112 C C 128 C C table 18. epm5128 i/o pin-outs (part 3 of 3) lab mc 68-pin plcc 68-pin pga lab mc 68-pin plcc 68-pin pga
736 altera corporation max 5000 pr ogrammab le logic de vice f amil y data sheet table 19. epm5130 dedicated pin-outs pin name 84-pin plcc 100-pin pga 100-pin pqfp input/clk 1 c7 16 input 2, 5, 6, 7, 36, 37, 38, 41, 42, 43, 44, 47, 48, 49, 78, 79, 80, 83, 84 a5, a7, a8, a9, a10, b5, b7, b9, c6, l7, l8, m5, m7, m9, n4, n5, n6, n7, n9 9, 10, 11, 14, 15, 16, 17, 20, 21, 22, 59, 60, 61, 64, 65, 66, 67, 70, 71, 72 gnd 19, 20, 39, 40, 61, 62, 81, 82 b8, c8, f2, f3, h11, h12, l6, m6 12, 13, 37, 38, 62, 63, 87, 88 vcc 3, 4, 23, 24, 45, 46, 65, 66 a6, b6, f12, f13, h1, h2, m8, n8 18, 19, 43, 44, 68, 69, 93, 94 table 20. epm5130 i/o pin-outs (part 1 of 3) lab mc 84-pin plcc 100-pin pga 100-pin pqfp lab mc 84-pin plcc 100-pin pga 100-pin pqfp a 1 8 b13 1 b 17 14 a4 23 2 9 c12 2 18 15 b4 24 3 10 a13 3 19 16 a3 25 4 11 b12 4 20 17 a2 26 5 12 a12 5 21 18 b3 27 6 13 b11 6 22 21 a1 28 7 C a11 7 23 C b2 29 8 C b10 8 24 C b1 30 9 C C C 25 C C C 10 C C C 26 C C C 11 C C C 27 C C C 12 C C C 28 C C C 13 C C C 29 C C C 14 C C C 30 C C C 15 C C C 31 C C C 16 C C C 32 C C C
altera corporation 737 max 5000 pr ogrammab le logic de vice f amil y data sheet 9 max 5000 c 33 22 c2 31 e 65 50 m1 51 34 25 c1 32 66 51 l2 52 35 26 d2 33 67 52 n1 53 36 27 d1 34 68 53 m2 54 37 28 e2 35 69 54 n2 55 38 29 e1 36 70 55 m3 56 39 C f1 39 71 C n3 57 40 C g2 40 72 C m4 58 41 C C C 73 C C C 42 C C C 74 C C C 43 C C C 75 C C C 44 C C C 76 C C C 45 C C C 77 C C C 46 C C C 78 C C C 47 C C C 79 C C C 48 C C C 80 C C C d 49 30 g3 41 f 81 56 n10 73 50 31 g1 42 82 57 m10 74 51 32 h3 45 83 58 n11 75 52 33 j1 46 84 59 n12 76 53 34 j2 47 85 60 m11 77 54 35 k1 48 86 63 m13 78 55 C k2 49 87 C m12 79 56 C l1 50 88 C m13 80 57 C C C 89 C C C 58 C C C 90 C C C 59 C C C 91 C C C 60 C C C 92 C C C 61 C C C 93 C C C 62 C C C 94 C C C 63 C C C 95 C C C 64 C C C 96 C C C table 20. epm5130 i/o pin-outs (part 2 of 3) lab mc 84-pin plcc 100-pin pga 100-pin pqfp lab mc 84-pin plcc 100-pin pga 100-pin pqfp
738 altera corporation max 5000 pr ogrammab le logic de vice f amil y data sheet g 97 64 l12 81 h 113 72 g11 91 98 67 l13 82 114 73 g13 92 99 68 k12 83 115 74 f11 95 100 69 k13 84 116 75 e13 96 101 70 j12 85 117 76 e12 97 102 71 j13 86 118 77 d13 98 103 C h13 89 119 C d12 99 104 C g12 90 120 C c13 100 105 C C C 121 C C C 106 C C C 122 C C C 107 C C C 123 C C C 108 C C C 124 C C C 109 C C C 125 C C C 110 C C C 126 C C C 111 C C C 127 C C C 112 C C C 128 C C C table 20. epm5130 i/o pin-outs (part 3 of 3) lab mc 84-pin plcc 100-pin pga 100-pin pqfp lab mc 84-pin plcc 100-pin pga 100-pin pqfp
altera corporation 739 max 5000 pr ogrammab le logic de vice f amil y data sheet 9 max 5000 table 21. epm5192 dedicated pin-outs pin name 84-pin plcc 84-pin pga input/clk 1 a6 input 2, 41, 42, 43, 44, 83, 84 a5, k6, j6, j7, l7, c7, c6 gnd 18, 19, 39, 40, 60, 61, 81, 82 a7, b7, e1, e2, g10, g11, k5, l5 vcc 3, 24, 45, 66 b5, e10, g2, k7 table 22. epm5192 i/o pin-outs (part 1 of 4) lab mc 84-pin plcc 84-pin pga lab mc 84-pin plcc 84-pin pga a 1 4 c5 b 17 12 c2 2 5 a4 18 13 b1 3 6 b4 19 14 c1 4 7 a3 20 15 d2 5 8 a2 21 C C 6 9 b3 22 C C 7 10 a1 23 C C 8 11 b2 24 C C 9 C C 25 C C 10 C C 26 C C 11 C C 27 C C 12 C C 28 C C 13 C C 29 C C 14 C C 30 C C 15 C C 31 C C 16 C C 32 C C
740 altera corporation max 5000 pr ogrammab le logic de vice f amil y data sheet c 33 16 d1 e 65 27 h2 34 17 e3 66 28 j1 35 20 f2 67 29 k1 36 21 f3 68 30 j2 37 C C 69 C C 38 C C 70 C C 39 C C 71 C C 40 C C 72 C C 41 C C 73 C C 42 C C 74 C C 43 C C 75 C C 44 C C 76 C C 45 C C 77 C C 46 C C 78 C C 47 C C 79 C C 48 C C 80 C C d 49 22 g3 f 81 31 l1 50 23 g1 82 32 k2 51 25 f1 83 33 k3 52 26 h1 84 34 l2 53 C C 85 35 l3 54 C C 86 36 k4 55 C C 87 37 l4 56 C C 88 38 j5 57 C C 89 C C 58 C C 90 C C 59 C C 91 C C 60 C C 92 C C 61 C C 93 C C 62 C C 94 C C 63 C C 95 C C 64 C C 96 C C table 22. epm5192 i/o pin-outs (part 2 of 4) lab mc 84-pin plcc 84-pin pga lab mc 84-pin plcc 84-pin pga
altera corporation 741 max 5000 pr ogrammab le logic de vice f amil y data sheet 9 max 5000 g 97 46 l6 i 129 58 h11 98 47 l8 130 59 f10 99 48 k8 131 62 g9 100 49 l9 132 63 f9 101 50 l10 133 C C 102 51 k9 134 C C 103 52 l11 135 C C 104 53 k10 136 C C 105 C C 137 C C 106 C C 138 C C 107 C C 139 C C 108 C C 140 C C 109 C C 141 C C 110 C C 142 C C 111 C C 143 C C 112 C C 144 C C h 113 54 j10 j 145 64 f11 114 55 k11 146 65 e11 115 56 j11 147 67 e9 116 57 h10 148 68 d11 117 C C 149 C C 118 C C 150 C C 119 C C 151 C C 120 C C 152 C C 121 C C 153 C C 122 C C 154 C C 123 C C 155 C C 124 C C 156 C C 125 C C 157 C C 126 C C 158 C C 127 C C 159 C C 128 C C 160 C C table 22. epm5192 i/o pin-outs (part 3 of 4) lab mc 84-pin plcc 84-pin pga lab mc 84-pin plcc 84-pin pga
742 altera corporation max 5000 pr ogrammab le logic de vice f amil y data sheet k 161 69 d10 l 177 73 a11 162 70 c11 178 74 b10 163 71 b11 179 75 b9 164 72 c10 180 76 a10 165 C C 181 77 a9 166 C C 182 78 b8 167 C C 183 79 a8 168 C C 184 80 b6 169 C C 185 C C 170 C C 186 C C 171 C C 187 C C 172 C C 188 C C 173 C C 189 C C 174 C C 190 C C 175 C C 191 C C 176 C C 192 C C table 22. epm5192 i/o pin-outs (part 4 of 4) lab mc 84-pin plcc 84-pin pga lab mc 84-pin plcc 84-pin pga
altera part number search literature licensing buy on-line download home | products | support | system solutions | technology center | education & events | corporate | buy on-line results for: epm5192* 0 part numbers found and 9 obsolete part numbers found obsolete part numbers part number format buying altera devices part number last order date last ship date replacement notes epm5192gc-2 9/30/96 12/31/96 epm5192gc-1 adv 9609 epm5192gc 9/30/96 12/31/96 epm5192gc-1 adv 9609 epm5192gm883b (5962-9206201myx) 1/31/96 3/31/96 no direct replacement pdn 9513 epm5192gm883b-2 (5962-9206202myx) 1/31/96 3/31/96 no direct replacement pdn 9513 epm5192gm 1/31/96 3/31/96 no direct replacement pdn 9513 epm5192jc-2 9/30/96 12/31/96 epm5192jc-1 adv 9609 epm5192jc 9/30/96 12/31/96 epm5192jc-1 adv 9609 epm5192ji 9/30/96 12/31/96 epm5192li adv 9609 epm5192lc-2 9/30/96 12/31/96 epm5192lc-1 adv 9609 advanced help please give us feedback sign up for e-mail updates home | products | support | system solutions | technology center | education & events | corporate | buy on-line contact us | new user | site map | privacy | legal notice copyright ? 1995-2004 altera corporation, 101 innovation drive, san jose, california 95134, usa http://www.altera.com/cgi-bin/devsearch.pl?searchtext=&docsetconstraints=&col=corp&qt=epm5192*&scope=0 [9/3/2004 10:06:23 am]
altera part number search literature licensing buy on-line download home | products | support | system solutions | technology center | education & events | corporate | buy on-line results for: epm5064* 0 part numbers found and 4 obsolete part numbers found obsolete part numbers part number format buying altera devices part number last order date last ship date replacement notes epm5064jc-2 9/30/96 12/31/96 epm5064jc-1 adv 9609 epm5064jc 9/30/96 12/31/96 epm5064jc-1 adv 9609 epm5064ji 9/30/96 12/31/96 epm5064li adv 9609 epm5064jm 1/31/96 3/31/96 no direct replacement pdn 9513 advanced help please give us feedback sign up for e-mail updates home | products | support | system solutions | technology center | education & events | corporate | buy on-line contact us | new user | site map | privacy | legal notice copyright ? 1995-2004 altera corporation, 101 innovation drive, san jose, california 95134, usa http://www.altera.com/cgi-bin/devsearch.pl?searchtext=&docsetconstraints=&col=corp&qt=epm5064*&scope=0 [9/3/2004 10:06:14 am]
altera part number search literature licensing buy on-line download home | products | support | system solutions | technology center | education & events | corporate | buy on-line results for: epm5128* 0 part numbers found and 13 obsolete part numbers found obsolete part numbers part number format buying altera devices part number last order date last ship date replacement notes epm5128gc-2 9/30/96 12/31/96 epm5128gc-1 adv 9609 epm5128gc 9/30/96 12/31/96 epm5128gc-1 adv 9609 epm5128gm883b (5962-8946801xc) 1/31/96 3/31/96 no direct replacement pdn 9513 EPM5128GM883B-2 1/31/96 3/31/96 no direct replacement pdn 9513 epm5128gm 1/31/96 3/31/96 no direct replacement pdn 9513 epm5128jc-2 9/30/96 12/31/96 epm5128jc-1 adv 9609 epm5128jc 9/30/96 12/31/96 epm5128jc-1 adv 9609 epm5128ji-2 9/30/96 12/31/96 epm5128li-2 adv 9609 epm5128ji 9/30/96 12/31/96 epm5128li-2 adv 9609 epm5128jm883b (5962-8946801) 7/30/93 12/31/93 no direct replacement - epm5128jm 1/31/96 3/31/96 no direct replacement pdn 9513 epm5128li-1 9/30/96 12/31/96 no direct replacement pdn 9610 epm5128li 9/30/96 12/31/96 epm5128li-2 adv 9609 advanced help please give us feedback sign up for e-mail updates home | products | support | system solutions | technology center | education & events | corporate | buy on-line contact us | new user | site map | privacy | legal notice copyright ? 1995-2004 altera corporation, 101 innovation drive, san jose, california 95134, usa http://www.altera.com/cgi-bin/devsearch.pl?searchtext=&docsetconstraints=&col=corp&qt=epm5128*&scope=0 [9/3/2004 10:06:18 am]
altera part number search literature licensing buy on-line download home | products | support | system solutions | technology center | education & events | corporate | buy on-line results for: epm5130* 0 part numbers found and 20 obsolete part numbers found obsolete part numbers part number format buying altera devices part number last order date last ship date replacement notes epm5130gc-2 9/30/96 12/31/96 epm5130gc-1 adv 9609 epm5130gi 9/30/96 12/31/96 no direct replacement pdn 9610 epm5130gm883b (5962-9314401mzx) 1/31/96 3/31/96 no direct replacement pdn 9513 epm5130gm883b-2 (5962-9314402mzx) 1/31/96 3/31/96 no direct replacement pdn 9513 epm5130gm 1/31/96 3/31/96 no direct replacement pdn 9513 epm5130jc-2 9/30/96 12/31/96 epm5130jc-1 adv 9609 epm5130ji-2 9/30/96 12/31/96 no direct replacement pdn 9610 epm5130ji 9/30/96 12/31/96 no direct replacement pdn 9610 epm5130jm 1/31/96 3/31/96 no direct replacement pdn 9513 epm5130lc-2 9/30/96 12/31/96 epm5130lc-1 adv 9609 epm5130li-2 9/30/96 12/31/96 no direct replacement pdn 9610 epm5130li 9/30/96 12/31/96 no direct replacement pdn 9610 epm5130qc-2 9/30/96 12/31/96 epm5130qc-1 adv 9609 epm5130qi 9/30/96 12/31/96 no direct replacement pdn 9610 epm5130wc-1 9/30/96 12/31/96 epm5130qc-1 adv 9609 epm5130wc-2 9/30/96 12/31/96 epm5130qc-1 adv 9609 epm5130wc 9/30/96 12/31/96 epm5130qc adv 9609 epm5130wm883b (5962-9314401mxx) 10/31/96 12/31/96 no direct replacement pdn 9513 epm5130wm883b-2 (5962-9314402mxx) 10/31/96 12/31/96 no direct replacement pdn 9513 epm5130wm 10/31/96 12/31/96 no direct replacement pdn 9513 advanced help please give us feedback sign up for e-mail updates http://www.altera.com/cgi-bin/devsearch.pl?searc...&docsetconstraints=&col=corp&qt=epm5130*&scope=0 (1 of 2) [9/3/2004 10:06:21 am]
altera part number search home | products | support | system solutions | technology center | education & events | corporate | buy on-line contact us | new user | site map | privacy | legal notice copyright ? 1995-2004 altera corporation, 101 innovation drive, san jose, california 95134, usa http://www.altera.com/cgi-bin/devsearch.pl?searc...&docsetconstraints=&col=corp&qt=epm5130*&scope=0 (2 of 2) [9/3/2004 10:06:21 am]
altera part number search literature licensing buy on-line download home | products | support | system solutions | technology center | education & events | corporate | buy on-line results for: epm5032* 0 part numbers found and 19 obsolete part numbers found obsolete part numbers part number format buying altera devices part number last order date last ship date replacement notes epm5032dc-17 9/30/96 12/31/96 epm5032dc-15 adv 9609 epm5032dc-25 9/30/96 12/31/96 epm5032dc-20 adv 9609 epm5032di-25 9/30/96 12/31/96 epm5032pi-25 adv 9609 epm5032dm-25 1/31/96 3/31/96 no direct replacement pdn 9513 epm5032dm883b (5962-9061102xa) 1/31/96 3/31/96 no direct replacement pdn 9513 epm5032jc-17 9/30/96 12/31/96 epm5032jc-15 adv 9609 epm5032jc-25 9/30/96 12/31/96 epm5032jc-20 adv 9609 epm5032ji-20 9/30/96 12/31/96 no direct replacement pdn 9610 epm5032ji-25 9/30/96 12/31/96 epm5032li-25 adv 9609 epm5032jm-25 1/31/96 3/31/96 no direct replacement pdn 9513 epm5032jm883b 7/30/93 12/31/93 no direct replacement - epm5032jm 7/30/93 12/31/93 no direct replacement - epm5032lc-17 9/30/96 12/31/96 epm5032lc-15 adv 9609 epm5032lc-25 9/30/96 12/31/96 epm5032lc-20 adv 9609 epm5032pc-17 9/30/96 12/31/96 epm5032pc-15 adv 9609 epm5032sc-15 6/30/97 12/31/97 no direct replacement pdn 9624 epm5032sc-17 9/30/96 12/31/96 short term epm5032sc-15, long term no direct replacement adv 9609 epm5032sc-20 9/30/96 12/31/96 short term epm5032sc-15, long term no direct replacement adv 9609 epm5032sc-25 9/30/96 12/31/96 short term epm5032sc-15, long term no direct replacement adv 9609 advanced help please give us feedback sign up for e-mail updates http://www.altera.com/cgi-bin/devsearch.pl?searc...&docsetconstraints=&col=corp&qt=epm5032*&scope=0 (1 of 2) [9/3/2004 10:06:10 am]
altera part number search home | products | support | system solutions | technology center | education & events | corporate | buy on-line contact us | new user | site map | privacy | legal notice copyright ? 1995-2004 altera corporation, 101 innovation drive, san jose, california 95134, usa http://www.altera.com/cgi-bin/devsearch.pl?searc...&docsetconstraints=&col=corp&qt=epm5032*&scope=0 (2 of 2) [9/3/2004 10:06:10 am]

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